Principal/Sr. Principal Digital Verification Engineer (FGPA/ASIC), Beavercreek, Oh

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Beavercreek, OH

Requisition ID: R10086335
Category: Engineering
Location: Beavercreek, OH, USA
Citizenship Required: United States Citizenship
Clearance Type: Top Secret
Telecommute: No- Teleworking not available for this position
Shift: 1st Shift (United States of America)
Travel Required: Yes, 10% of the Time
Relocation Assistance: Relocation assistance may be available
Positions Available: 2

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people’s lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation’s history – from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they’re making history.

Join Northrop Grumman Mission Systems Sector (NGMS) a leading global provider of secure software-defined, hardware enabled mission systems. Our company is pioneering capabilities in a wide variety of technologies that keep our nation and our allies safe from undersea to space and cyberspace. 

 Define Possible In Ohio

Essential Duties:

As a Digital Verification Engineer you will support ASIC and FPGA product development. In this capacity, you will work closely with design and verification engineers and will utilize your knowledge of modern verification methods, tools and techniques. The individual will perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog and Cadence Xcelium simulation tool. This task includes but not limited to development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc. This candidate will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.

This position may be filled as a Principal Digital Verification Engineer or a Sr. Principal Digital Verification Engineer

Basic Qualifications for Principal Digital Verification Engineer:

• Bachelor of Science (BS) degree in science, engineering, or related discipline with 5 years of experience; or 3 years of relevant experience with a Masters (MS) degree; or 0 years with a PhD
• Knowledge of Universal Verification Methodology (UVM).
• Experience developing test plans, participating in reviews, test development and RTL debugging.

• Clearance: Must be a US Citizen with the ability to obtain and maintain a Top Secret clearance.

Basic Qualifications for Principal Digital Verification Engineer:

• Bachelor of Science (BS) degree in science, engineering, or related discipline with 9 years of experience; or 7 years of relevant experience with a Masters (MS) degree; or 4 years with a PhD;
• Knowledge of Universal Verification Methodology (UVM).
• Experience developing test plans, participating in reviews, test development and RTL debugging.

• Clearance: Must be a US Citizen with the ability to obtain and maintain a Top Secret clearance.

Preferred Qualifications:

• Experience in HDL (VHDL/Verilog) and SystemVerilog (HVL).
• Experience with SystemVerilog Assertions (SVA).
• Familiarity with a coverage-driven verification methodology from planning through closure.
• Knowledge of industry standard interfaces.
• Experience with object oriented programming languages and concepts.
• Experience with Mentor Graphics and/or Cadence Verification tools.
• FPGA/ASIC Design experience.
• Knowledge of digital signal processing.
• Experience with scripting languages (Bash, Perl, Python, Tcl).
• Active TS/SCI security clearance.

This position offers the option of a 9/80 work schedule. The 9/80 schedule allows employees who work nine-hour days Monday through Thursday to take every other Friday off.

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Salary Range: $104,700 USD – $157,100 USD
Salary Range 2: $129,800 USD – $194,800 USD

Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The health and safety of our employees and their families is a top priority. The company encourages employees to remain up-to-date on their COVID-19 vaccinations. U.S. Northrop Grumman employees may be required, in the future, to be vaccinated or have an approved disability/medical or religious accommodation, pursuant to future court decisions and/or government action on the currently stayed federal contractor vaccine mandate under Executive Order 14042 https://www.saferfederalworkforce.gov/contractors/.

Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.

Northrop Grumman / Equal Opportunity Employer

JBNGJ-R10086335 2023.01.14

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